(1) Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory device, and more particularly, to a method of forming a dynamic random access memory device having a simple geometry active area, self-aligned crown capacitors, and simultaneous formation of bit lines and polysilicon plugs.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) devices are widely used in the art. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. Conventional DRAM capacitor fabrications consist of a contact hole patterning for capacitor nodes and a polysilicon patterning for lower plates of the capacitors. As the line width of DRAM's shrinks, the aspect ratio of the contact holes increases and the effective area of the capacitors decreases. Also, the traditional s-shape of the active area of a DRAM causes difficulties in the patterning of twisted bit lines. Improvements of the complicated active area, contact technology, and novel capacitors are in great demand for DRAM manufacturing.
U.S. Pat. No. 4,966,870 to Barber et al and U.S. Pat. No. 5,944,682 to Cronin et al teach methods of forming borderless contacts using a two-step etching process in which there is high selectivity to oxide with respect to silicon nitride. U.S. Pat. No. 5,258,096 to Sandhu et al teaches a method using a conductive layer as an etch stop for a self-aligned contact. U.S. Pat. No. 5,466,636 to Cronin et al shows another method of making a borderless contact. U.S. Pat. No. 5,491,104 to Lee et al teaches using polysilicon as a protective etch stop layer in forming a fin-shaped capacitor. U.S. Pat. No. 5,491,103 to Ahn et al teaches a method of forming a crown capacitor and bit line contacts.